OWC 64GB (4x16GB) DDR3 1333 PC3-10600 CL9 2Rx4 240-pin 1.5V ECC Registered DIMM memory upgrade
- 64GB (4 x 16GB)
- 240-Pin DDR3 ECC RD…
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OWC
Four 16 GB DDR3 ECC registered DIMMs at 1333 MHz for Lenovo System x3950 X5
Capacity 64GB (4 x 16GB)
This 64 GB kit contains four 16 GB DDR3 1333 modules built to PC3-10600 CL9 timings at 1.5 V. Each stick is a 240-pin registered ECC RDIMM with 2Rx4 organisation. The set is validated for the Lenovo System x3950 X5 and replaces Lenovo part numbers 03X3813 and 0A89413.
No heat spreader is fitted so airflow from the server chassis handles cooling directly across the DRAM. Registered buffering reduces electrical load on the memory controller, helping keep power draw predictable in multi-DIMM configurations. Operation stays within standard DDR3 1.5 V limits.
Four populated slots are required so the target platform must expose at least that many 240-pin DDR3 sockets. The modules are incompatible with unbuffered desktop boards and cannot be mixed with non-ECC memory. Buyers needing consumer DDR3 or higher-density single modules should look elsewhere.
| Brand | OWC |
|---|---|
| Part Number | 1R3D32R4064S |
| Capacity | 64GB (4 x 16GB) |
| Type | 240-Pin DDR3 ECC RDIMM |
| Speed | DDR3 1333 (PC3 10600) |
| CAS Latency | CL9 |
| Voltage | 1.5V |
| ECC | Yes |
| Buffered/Registered | Registered |
| Rank | 2Rx4 |
| Heat Spreader | No |
| Compatible System | Lenovo System x3950 X5 |
Druge verzije ovog modela
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Power down the server, open the chassis, and seat each 240-pin module firmly until the ejector clips click; the step often missed is populating all four slots in the matched-channel order shown in the x3950 X5 service guide so the 64 GB kit runs at the rated PC3-10600 speed.
The modules have no heat spreaders and no moving parts, so no routine maintenance is required; replacement is only necessary if a DIMM fails, at which point OWC's Advanced Replacement programme supplies a new 16 GB RDIMM of the same PC3-10600 CL9 specification.
The memory bus tops out at 1333 MT/s and CL9 latency, so bandwidth and latency ceilings are reached before the 1.5 V registered DIMMs hit any thermal or power limit.
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