IBM
IBM 46W9136 Xeon E5-2680 v2 10-core 2.8 GHz 25 MB L3 115 W server processor
A 10-core Xeon server processor running at 2.8 GHz with 25 MB L3 cache and 115 W TDP, supporting DDR3 1866 memory via FCLGA2011 socket
- Integrated Memory Controller SpeedDDR3 1866
- 10 cores handle parallel workloads
- 8 GHz base clock drives compute speed
- 25 MB L3 cache reduces memory latency
- DDR3 1866 memory controller supports high-throughput RAM
IBM Xeon E5-2680 v2 10-Core Processor
This refurbished IBM server processor carries the 46W9136 part number and delivers ten cores running at 2.8 GHz with a 25 MB L3 cache. Built on a 22 nm process, it fits the FCLGA2011 socket and operates within a 115 W thermal envelope. The integrated memory controller supports DDR3 at 1866 MT/s and the QuickPath Interconnect runs at 8 GT/s.
Suits dense dual-socket servers needing proven
The ten-core design handles virtualisation, database and compute workloads that benefit from high thread counts and large cache. The 115 W TDP requires adequate server cooling and a compatible FCLGA2011 platform. Buyers needing more than ten cores or a different memory generation should evaluate other options.
Høydepunkter
- 10 cores handle parallel workloads
- 8 GHz base clock drives compute speed
- 25 MB L3 cache reduces memory latency
- DDR3 1866 memory controller supports high-throughput RAM
Spesifikasjoner
| Integrated Memory Controller Speed | DDR3 1866 |
|---|---|
| Fraktvekt | 0.91 kg |
| Pakkestørrelse | 127 × 127 × 51 mm |
Spørsmål om denne varen
Should I pick this 10-core 2.8 GHz Xeon or a lower-core model for a dual-socket server?
This 46W9136 delivers 10 cores at 2.8 GHz with 25 MB L3 cache and 115 W TDP; a lower-core part would reduce parallel throughput but also lower power draw and heat in a dual-socket chassis.
What does the 2.8 GHz clock mean once the CPU is installed in a live server?
In a real machine the 2.8 GHz base frequency runs sustained across all 10 cores within the 115 W envelope, while the DDR3 1866 memory controller keeps data flowing to each core without downclocking.
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