OWC 16GB DDR3L 1600 ECC Registered RDIMM 2Rx4 1.35V 240-pin memory upgrade
- 16GB
- 240-Pin DDR3L ECC R…
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OWC
32 GB dual-channel DDR3L ECC registered kit at 1600 MHz for Cisco UCS C24 M3, C240 M3 and C420 M3 servers
Capacity 32GB (2 x 16GB)
This 32 GB upgrade kit contains two 16 GB DDR3L 1600 registered DIMMs built for Cisco UCS C24 M3, C240 M3 and C420 M3 servers. ECC and registered operation provide the error correction and signal integrity required by enterprise workloads. The modules run at 1.35 V and conform to the PC3L-12800 CL11 2Rx4 specification. They replace Cisco part numbers UCSMR1X162RYA, UCSMR1X162RYARF and UCSMR2X162RYE.
Each module uses the standard 240-pin DDR3L RDIMM layout with no heat spreader, fitting directly into the compatible Cisco UCS chassis. Registered buffering reduces electrical load on the memory controller, allowing larger capacities per channel. The 1.35 V DDR3L voltage lowers power draw compared with standard DDR3. Buyers needing unbuffered or load-reduced DIMMs cannot use this kit.
The kit upgrades or expands memory in the listed Cisco UCS M3 servers, delaying a full platform refresh. It is not compatible with standard desktop computers, consumer motherboards or systems that require unbuffered or load-reduced memory. Organisations running virtualisation, databases or high-density workloads on these platforms gain capacity without changing hardware generations.
| Brand | OWC |
|---|---|
| Part Number | 1R6T32R4032P |
| Capacity | 32GB (2 x 16GB) |
| Type | 240-Pin DDR3L ECC RDIMM |
| Speed | DDR3L 1600 (PC3L 12800) |
| CAS Latency | CL11 |
| Voltage | 1.35V |
| ECC | Yes |
| Buffered/Registered | Registered |
| Rank | 2Rx4 |
| Heat Spreader | No |
| Compatible System | Cisco UCS C24 M3 Cisco UCS C240 M3 Cisco UCS C420 M3 |
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PC3L-12800 is the JEDEC standard name for DDR3L 1600, showing the modules run at 1600 MHz with a CL11 latency at 1.35 V.
Yes, the kit is listed as compatible with the Cisco UCS C24 M3, C240 M3 and C420 M3, using the same 240-pin DDR3L RDIMM form factor those servers require.
Populate the lowest-numbered DIMM slots for each CPU channel first, following the server's silkscreen or manual, so the registered ECC modules initialise in the supported rank sequence.
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