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Refurbished Intel Xeon server CPU, square ceramic package with gold contacts and metal heat spreader

IBM

IBM 88Y6112 Xeon Octacore E78837 2.66GHz 24MB 130W server processor

SKU CH-53GZ-NKKPT MPN 88Y6112

Refurbished octa-core Xeon server processor running at 2.66 GHz with 24 MB cache, 6.4 GT/s QPI, DDR3-1066 memory support and a 130 W TDP in an LGA 1567 socket

  • Integrated Memory Controller SpeedDDR3 1066
  • Eight cores handle parallel workloads efficiently
  • 24 MB Smart Cache reduces memory latency
  • 4 GT/s QPI enables fast inter-socket links
  • DDR3-1066 controller integrates memory management

Refurbished 8-core Xeon server processor

This IBM 88Y6112 module contains an Intel Xeon E78837 running at 2.66 GHz with eight cores and 24 MB of Smart Cache. It fits a Socket LGA 1567 platform and draws 130 W. The part is sold as a processor only, without a heatsink or additional accessories.

DDR3-1066 memory controller limits upgrade path

The integrated controller supports DDR3 at 1066 MT/s, so systems requiring faster memory speeds or newer DDR generations cannot use this CPU. Buyers needing higher memory bandwidth or a different socket type should select another processor.

Pluspunten

  • Eight cores handle parallel workloads efficiently
  • 24 MB Smart Cache reduces memory latency
  • 4 GT/s QPI enables fast inter-socket links
  • DDR3-1066 controller integrates memory management

Specificaties

Integrated Memory Controller SpeedDDR3 1066
Verzendgewicht0.91 kg
Pakketafmetingen127 × 127 × 51 mm

Vragen over dit artikel

How does the 2.66 GHz clock speed affect performance once the processor is installed in a server?

The 2.66 GHz base frequency sets the execution pace for each of the eight cores, giving consistent throughput for multi-threaded server workloads such as virtualization or database tasks.

What does the 6.4 GT/s QPI link limit in a multi-socket system?

The 6.4 GT/s QuickPath Interconnect caps the maximum data rate between this processor and other CPUs or the chipset, defining the peak bandwidth available for cache coherency and memory traffic across sockets.

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