OWC 64GB DDR4 3200MHz PC4-25600 CL22 4RX4 ECC LRDIMM 1.2V 288-pin Server RAM
- 64GB
- 288-Pin DDR4 ECC LR…
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OWC
A 128GB DDR4 2933 ECC load-reduced DIMM for HP Apollo 4200 and 6500 Gen10 servers
Capacity 128GB
This 128GB DDR4 LRDIMM module is built for HP Apollo 4200 Gen10 and 6500 Gen10 servers. It delivers ECC Load Reduced operation at 2933 MT/s with CL21 latency. The single 4Rx4 stick fits 288-pin slots in compatible workstation and NAS platforms. It is not suitable for standard desktop computers or unbuffered memory configurations.
Operating at 1.2V, the module runs without a heat spreader in typical server airflow. Load Reduced buffering lowers electrical load on the memory controller during sustained workloads. JEDEC-compliant design ensures stable thermals at rated speed. No active cooling or fan requirements are specified for this component.
The 288-pin ECC LRDIMM form factor installs directly into matching DIMM slots on supported HP Apollo systems. Backward compatibility with 2133, 2400 and 2666 MT/s buses allows mixed-speed population where the platform permits. Modules cannot be mixed with unbuffered or standard registered ECC DIMMs. Replaces multiple HP part numbers including P19047 and P11040 series.
| Brand | OWC |
|---|---|
| Part Number | 2L9D44R4128G |
| Capacity | 128GB |
| Type | 288-Pin DDR4 ECC LRDIMM |
| Speed | DDR4 2933 (PC4 23400) |
| CAS Latency | CL21 |
| Voltage | 1.2V |
| ECC | Yes |
| Buffered/Registered | Load Reduced |
| Rank | 4Rx4 |
| Heat Spreader | No |
| Compatible System | HP Apollo 4200 Gen10 HP Apollo 6500 Gen10 |
Other versions of this model
Same family, different memory, cooler or clock — compare before you commit.
Align the notch on the 288-pin edge connector with the slot key, press straight down until both retention clips click, and ensure the 1.2V LRDIMM is not mixed with unbuffered or registered DIMMs — that is the step most often missed.
No routine maintenance is required; if a memory error appears, run the server diagnostics and replace the single 128GB module if it fails, keeping the load-reduced ECC type consistent across the channel.
The DDR4 2933 MT/s data rate and CL21 latency set the throughput ceiling; sustained workloads will hit that bandwidth limit before the 1.2V voltage or thermal envelope becomes a constraint.
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