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Four silver DDR5 RDIMMs with black heat spreaders, 288-pin registered ECC modules

V-color

V-color OC R-DIMM DDR5 128GB (4×32GB) 7200MHz CL34 2Rx8 1.4V Registered ECC

SKU CH-J9DT-VPEKK

128 GB quad-channel DDR5 registered ECC kit runs at 7200 MHz CL34 on AMD TRX50 workstations

  • Capacity128GB (4 x 32GB)
  • Type288-Pin DDR5 RDIMM
  • SpeedDDR5 7200 (PC5 57600)
  • CAS LatencyCL34
  • Timing34-45-45-112
  • Voltage1.40V

Capacity 128GB (4 x 32GB)

  • 64GB (4 x 16GB)
  • 128GB (4 x 32GB)
  • 192GB (4 x 48GB)
  • 256GB (4 x 64GB)
  • 512GB (4 x 128GB)
  • 1TB (4 x 256GB)
  • 384GB (4 x 96GB)

Struck-through versions exist but are not stocked here.

Speed DDR5 7200 (PC5 57600)

Struck-through versions exist but are not stocked here.

Rank 2Rx8

Struck-through versions exist but are not stocked here.

  • 128GB quad-channel capacity for heavy workloads
  • 7200MHz DDR5 speed with CL34 latency
  • Registered ECC with on-die error correction
  • AMD EXPO profile for TRX50 workstations
  • Hynix ICs on 10-layer PCB with thermal sensor

Target Workstation Memory

This 128GB kit uses four 32GB DDR5 registered DIMMs built for AMD TRX50 workstation motherboards. Registered ECC with on-die error correction protects data integrity in professional workloads. The modules run at 7200MHz with CL34 timings via an AMD EXPO profile. They are not compatible with desktop PCs or laptops.

Thermals and Power in Normal Use

A 10-layer PCB and aluminium heat spreader dissipate heat while the modules operate at 1.40V. An on-board thermal sensor monitors temperature to prevent overheating during typical workstation tasks. Registered buffering reduces electrical load on the memory controller for stable signalling. Each Hynix IC is tested with automated sorting equipment for consistent quality.

Behaviour Under Sustained Load

The on-board PMIC manages power delivery across all four DIMMs during extended compute sessions. Dual 40-bit sub-channels per module maintain bandwidth efficiency when all ranks are active. Registered ECC continues correcting errors without halting the system under heavy memory pressure. The EXPO profile keeps timings stable at 34-45-45-112 throughout prolonged operation.

Highlights

  • 128GB quad-channel capacity for heavy workloads
  • 7200MHz DDR5 speed with CL34 latency
  • Registered ECC with on-die error correction
  • AMD EXPO profile for TRX50 workstations
  • Hynix ICs on 10-layer PCB with thermal sensor

Specifications

BrandV-Color
SeriesOC R-DIMM
ModelTRA532G72D834Q
Part NumberTRA532G72D834Q
Capacity128GB (4 x 32GB)
Type288-Pin DDR5 RDIMM
SpeedDDR5 7200 (PC5 57600)
CAS LatencyCL34
Timing34-45-45-112
Voltage1.40V
ECCYes
Buffered/RegisteredRegistered
Rank2Rx8
BIOS/Performance ProfileAMD EXPO
ChipsetHynix IC
Heat SpreaderYes
FeaturesSupports ECC functionality to detect and correct data errors and features a built-in temperature-monitoring thermal sensor to prevent overheating, thereby enhancing memory reliability.
Operating temperature range: 0 to 85 °C

Other versions of this model

5 more in the same range

Same family, different memory, cooler or clock — compare before you commit.

Questions about this item

How do I install the 288-Pin DDR5 RDIMM modules on a TRX50 motherboard, and what step is often missed?

Align the notch on each 288-Pin DDR5 RDIMM with the slot key, press firmly until both side latches click, then enable the AMD EXPO profile in BIOS to run at 7200MHz CL34 1.40V; skipping the EXPO enable leaves the kit at JEDEC defaults.

What maintenance or replacement will the 128GB (4×32GB) kit need during its service life?

The modules carry a built-in thermal sensor and on-board PMIC; no user-serviceable parts exist, so replacement only occurs if a DIMM fails ECC correction or the sensor reports sustained overheating.

What limit appears first when the 7200MHz CL34 2Rx8 kit runs sustained workloads?

The on-board PMIC and thermal sensor manage power and temperature; the first practical ceiling is the 1.40V voltage ceiling combined with the thermal sensor triggering throttling before data errors occur.

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