OWC 16GB DDR4 2933MHz ECC Registered RDIMM 2Rx8 CL21 1.2V 288pin Memory Upgrade
- 16GB
- 288-Pin DDR4 ECC RD…
OWC
16GB DDR4 2933MHz ECC registered RDIMM for Lenovo ThinkAgile HX2320 HX2321 HX3320 HX3321 servers
This 16GB DDR4 2933MHz module is built for Lenovo ThinkAgile HX2320 HX2321 HX3320 HX3321 and HX3520-G systems. It uses registered ECC technology required by Xeon SP Gen 2 servers and workstations. The 288-pin RDIMM will not work in standard desktop boards or alongside unbuffered memory. Buyers needing consumer DIMMs or non-ECC RAM should look elsewhere.
The module runs at the JEDEC standard 1.2V with CL21 latency and no heat spreader. Registered buffering adds a clock cycle for signal integrity under sustained server loads. Power consumption scales with the 2Rx8 rank configuration at the rated 2933MHz speed. Acoustic output is silent as the DIMM relies on chassis airflow.
This stick replaces Lenovo part numbers 01AG631 4ZC7A08708 and 4ZC7A08741. Backward compatibility covers 2133MHz 2400MHz and 2666MHz bus speeds so it can fill slots in mixed-speed configurations. The upgrade is worth it when expanding capacity for virtualization databases or NAS workloads on the listed ThinkAgile platforms.
| Brand | OWC |
|---|---|
| Part Number | 2R9D42R816GB |
| Capacity | 16GB |
| Type | 288-Pin DDR4 ECC RDIMM |
| Speed | DDR4 2933 (PC4 23400) |
| CAS Latency | CL21 |
| Voltage | 1.2V |
| ECC | Yes |
| Buffered/Registered | Registered |
| Rank | 2Rx8 |
| Heat Spreader | No |
| Compatible System | Lenovo ThinkAgile (Xeon SP Gen 2) HX2320 Lenovo ThinkAgile (Xeon SP Gen 2) HX2321 Lenovo ThinkAgile (Xeon SP Gen 2) HX3320 Lenovo ThinkAgile (Xeon SP Gen 2) HX3321 Lenovo ThinkAgile (Xeon SP Gen 2) HX3520-G |
其他版本
同系列產品,記憶體、散熱器或時脈不同 — 下單前請先比較。
Power off the server, open the chassis, align the notch on the 288pin module with the slot key, press firmly until the ejector tabs click shut, then verify in BIOS that the 16GB module registers at 2933MHz with ECC active.
No scheduled maintenance is required; the module has no heat spreader or moving parts. Replace only if memory diagnostics report uncorrectable ECC errors or the system fails to POST with the DIMM seated.
The registered buffer adds one clock cycle of latency, so the CL21 timing at 2933MHz becomes the throughput ceiling before thermal or voltage limits are reached.
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