A-Tech 128GB 4Rx4 DDR4 3200 ECC LRDIMM server RAM
- 128GB
- 288-Pin DDR4 SDRAM
A-Tech
256 GB dual-channel DDR4 server kit with two 128 GB ECC load-reduced DIMMs at 2933 MHz CL21 1.20 V
Capacity 256GB (2 x 128GB)
This A-Tech kit provides 256GB of DDR4 ECC LRDIMM memory across two 128GB modules. It is built for servers and workstations that require registered load-reduced DIMMs and cannot use standard desktop or laptop memory.
Each module operates at the standard DDR4 voltage of 1.20V without a heat spreader. The load-reduced design reduces electrical load on the memory bus, helping to maintain stable thermals and consistent power draw in multi-DIMM server configurations.
The modules use a 2S4Rx4 octal-rank x4 3DS/TSV organisation on a 288-pin interface. This specific rank structure and pin count dictate compatibility; only systems qualified for 8Rx4 LRDIMMs at this density will accept the kit.
| Brand | A-Tech |
|---|---|
| Series | A-Tech DDR4 Server Memory RAM |
| Model | A-Tech 128GB 2S4Rx4 PC4-2933Y-L |
| Part Number | AT128G2D4D2933LO4N12V |
| Capacity | 256GB (2 x 128GB) |
| Type | 288-Pin DDR4 SDRAM |
| Speed | DDR4 2933 (PC4 23400) |
| CAS Latency | CL21 |
| Voltage | 1.20V |
| ECC | Yes |
| Buffered/Registered | Load Reduced |
| Rank | 2S4Rx4 (8Rx4 3DS/TSV) |
| Multi-channel Kit | Dual Channel Kit |
| Chipset | Major Brand Chipset |
| Heat Spreader | No |
| Features | Major Brand Chips / Error Correcting Technology for Server Systems |
其他版本
同系列產品,記憶體、散熱器或時脈不同 — 下單前請先比較。
Power down the server, open the chassis, and align each 128 GB module with the 288-pin DDR4 slot. Seat both sticks in the matching channel pair indicated by the system manual so the dual-channel kit operates at 2933 MHz with ECC load-reduced buffering.
The modules have no heat spreaders and no moving parts, so routine maintenance is limited to keeping server airflow clean. If a module fails, the ECC load-reduced design will flag correctable errors; replace the affected 128 GB stick to restore full 256 GB capacity.
The CAS latency of CL21 at 1.20 V sets the timing ceiling; under continuous heavy traffic the memory controller will hit this latency boundary before thermal or voltage limits become a factor.
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