EN-Labs 11-001-366 PCIe x4 USB 3.2 10Gbps 5-port card
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ADATA
A 32GB DDR5 5600 ECC registered RDIMM with CL46 timing and on-die error correction for Xeon and Threadripper PRO platforms
This ADATA XPG module delivers 32GB of DDR5 5600 capacity in a single 288-pin RDIMM. It targets workstations and servers that require registered ECC memory for data integrity. The Registered design adds a register clock driver to stabilise heavy multi-DIMM configurations.
Operating at 1.10V, the module runs without a heat spreader and relies on chassis airflow for cooling. On-die ECC and side-band ECC provide error correction without extra power overhead. The temperature sensor protection monitors thermal conditions during sustained workloads.
A 30µ gold-plated connector resists oxidation over repeated insertions. Strictly selected ICs and the register clock driver support stable timing at 46-45-45 with CL46 latency. The bare PCB fits tight DIMM spacing where tall heat spreaders would interfere. Buyers needing unbuffered UDIMMs or higher frequency kits should look elsewhere.
| Brand | XPG |
|---|---|
| Model | AD5R560032G20-SHYA |
| Capacity | 32GB |
| Type | 288-Pin DDR5 RDIMM |
| Speed | DDR5 5600 (PC5 44800) |
| CAS Latency | CL46 |
| Timing | 46-45-45 |
| Voltage | 1.10V |
| ECC | Yes |
| Buffered/Registered | Registered |
| Heat Spreader | No |
| Features | Strictly selected high-quality ICs Register Clock Driver for stable performance On-die ECC & Side-band ECC error correction mechanisms 30µ gold plated connector & temperature sensor protection Supports Intel Xeon and AMD Ryzen Threadripper PRO series workstation platforms |
| 出貨重量 | 0.02 kg |
| 包裝尺寸 | 171 × 57 × 9 mm |
Align the module key with the slot, press firmly until both latches click, then verify in BIOS that the registered clock driver is detected at 5600 MT/s.
No scheduled maintenance is required; the 30µ gold-plated connectors and on-die ECC reduce wear, so replacement only occurs if a correctable error threshold is exceeded.
The thermal sensor on the RDIMM triggers throttling before voltage or timing margins are reached, capping sustained throughput to protect data integrity.
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