OWC 64GB (2x32GB) DDR3L 1600 CL11 4Rx4 240-pin 1.35V ECC Registered RDIMM memory upgrade
- 64GB (2 x 32GB)
- 240-Pin DDR3L ECC R…
OWC
128 GB DDR3L ECC registered kit in four 32 GB modules at 1600 MHz for Supermicro A+ servers
Capacity 128GB (4 x 32GB)
This 128GB kit contains four 32GB DDR3L 1600 CL11 registered DIMMs built for Supermicro A+ Server 2022TC, 2022TG, 4022G and 4042G systems. It is designed for workstation and server platforms that require ECC registered memory. It will not work in standard desktop computers or alongside unbuffered modules.
Each module runs at 1.35 volts under the PC3L-12800 JEDEC standard, reducing power draw and heat compared to standard DDR3. The registered buffer and ECC functionality add minimal overhead while maintaining data integrity. No heat spreaders are fitted, so airflow through the server chassis handles cooling.
The 240-pin DDR3L RDIMMs use a 4Rx4 organisation and must occupy slots that support registered ECC memory. Mixing with unbuffered DIMMs is not supported. The kit is validated for the listed Supermicro A+ Server series and complies with JEDEC and RoHS requirements.
| Brand | OWC |
|---|---|
| Part Number | 1R6T34R4128S |
| Capacity | 128GB (4 x 32GB) |
| Type | 240-Pin DDR3L ECC RDIMM |
| Speed | DDR3L 1600 (PC3L 12800) |
| CAS Latency | CL11 |
| Voltage | 1.35V |
| ECC | Yes |
| Buffered/Registered | Registered |
| Rank | 4Rx4 |
| Heat Spreader | No |
| Compatible System | Supermicro A+ Server 2022TC Series Supermicro A+ Server 2022TG Series Supermicro A+ Server 4022G Series Supermicro A+ Server 4042G Series |
其他版本
同系列產品,記憶體、散熱器或時脈不同 — 下單前請先比較。
Power off the server, open the chassis, align each 240-pin module with the DIMM slot notch, and press firmly until both retention clips click. The step often missed is populating all four channels in the order specified by the Supermicro A+ Server manual to enable quad-channel operation.
The modules have no heat spreaders and no moving parts, so no routine maintenance is required. Replacement is only needed if a module fails ECC error correction, which the registered design helps prevent by reducing electrical load on the memory controller.
The 1.35 V DDR3L voltage and CL11 latency set the thermal and timing envelope. Under sustained load the memory controller reaches its maximum sustainable bandwidth at PC3L-12800 before temperature or voltage limits become a factor.
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