OWC 64GB (8x8GB) DDR4 2666MHz CL19 ECC Registered RDIMM 1.2V 288-pin Server RAM
- 64GB (8 x 8GB)
- 288-Pin DDR4 ECC RD…
OWC
Eight 16 GB DDR4 2666 MHz ECC registered RDIMMs totalling 128 GB at 1.2 V CL19 for servers and workstations
Capacity 128GB (8 x 16GB)
This OWC kit delivers 128GB of DDR4 memory across eight 16GB registered DIMMs. It targets administrators upgrading workstations, servers or NAS systems that require ECC error correction and registered signalling. Standard desktop boards cannot use these modules, and they must not be mixed with unbuffered memory.
Each module operates at the standard DDR4 voltage of 1.2V and carries no heat spreader. The registered buffer and ECC logic add minimal overhead, so power draw stays within JEDEC limits for PC4-21300 parts. Passive cooling in a properly ventilated chassis is sufficient for normal server workloads.
The kit is validated against JEDEC specifications and RoHS directives, ensuring a warranty-safe upgrade. Modules automatically clock down to 2133MHz or 2400MHz when installed in platforms that do not support the full 2666MHz data rate, preserving stability without manual configuration.
| Brand | OWC |
|---|---|
| Part Number | 2R6D42R4128K |
| Capacity | 128GB (8 x 16GB) |
| Type | 288-Pin DDR4 ECC RDIMM |
| Speed | DDR4 2666 (PC4 21300) |
| CAS Latency | CL19 |
| Voltage | 1.2V |
| ECC | Yes |
| Buffered/Registered | Registered |
| Rank | 2Rx4 |
| Multi-channel Kit | Dual Channel Kit |
| Heat Spreader | No |
其他版本
同系列產品,記憶體、散熱器或時脈不同 — 下單前請先比較。
Power down the server, open the chassis, align each 288-pin module with the slot key, press firmly until the retention clips lock, and populate all eight slots following the motherboard's channel order; the step often missed is verifying the BIOS recognises all 128GB at 2666MHz after the first boot.
No scheduled maintenance is required; keep air pathways clear so the modules stay within the 1.2V operating envelope, and replace any stick only if the system logs uncorrectable ECC errors that persist after re-seating.
The registered buffer and CL19 latency set the effective throughput ceiling at the JEDEC PC4-21300 rate; sustained traffic that saturates this bandwidth will queue at the memory controller before thermal or voltage limits are reached.
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