OWC 64GB DDR4 2933MHz CL21 1.2V 288pin ECC Registered RDIMM memory upgrade
- 64GB
- 288-Pin DDR4 ECC RD…
OWC
128GB DDR4 2933MHz ECC registered RDIMM for Supermicro X11 server motherboards
This 128GB DDR4 2933MHz CL21 registered module targets Supermicro X11DPG-SN, X11DPH-I, X11DPH-T, X11DPH-Tq and X11DPi-N motherboards. It delivers error-correcting, buffered memory for workloads that demand data integrity and high capacity. The kit is not compatible with standard desktop boards or unbuffered DIMMs.
Operating at 1.2V, the module runs without a heat spreader and relies on chassis airflow for cooling. Registered buffering reduces electrical load on the memory controller, helping to keep power draw predictable during sustained server tasks. No active cooling is included or required by the specification.
The 288-pin DDR4 form factor fits the listed Supermicro server platforms and supports backward-compatible speeds of 2133MHz, 2400MHz and 2666MHz. ECC registration frees the memory controller from parity duties, while the 4Rx4 organisation maximises density per slot. Mixing with unbuffered memory is not supported.
| Brand | OWC |
|---|---|
| Part Number | 2R9D44R4128G |
| Capacity | 128GB |
| Type | 288-Pin DDR4 ECC RDIMM |
| Speed | DDR4 2933 (PC4 23400) |
| CAS Latency | CL21 |
| Voltage | 1.2V |
| ECC | Yes |
| Buffered/Registered | Registered |
| Rank | 4Rx4 |
| Heat Spreader | No |
| Compatible System | Supermicro Motherboard X11DPG-SN Supermicro Motherboard X11DPH-I Supermicro Motherboard X11DPH-T Supermicro Motherboard X11DPH-Tq Supermicro Motherboard X11DPi-N |
其他版本
同系列產品,記憶體、散熱器或時脈不同 — 下單前請先比較。
Power down the server, open the chassis, align the notch on the module with the slot key, press firmly until both ejector clips lock, then verify in BIOS that all 128GB are recognised at 2933MHz.
No scheduled maintenance is needed; ECC corrects single-bit errors on the fly, and the module should only be replaced if uncorrectable errors appear or a memory diagnostic reports a hard failure.
The registered buffer and 4Rx4 organisation add one clock cycle of latency, so the CL21 timing at 2933MHz becomes the primary latency ceiling before bandwidth or thermal limits are reached.
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